1. Field of the Invention
The present invention relates to a digital circuit which operates in accordance with a digital signal, and more particularly to a semiconductor device having one or a plurality of the digital circuits and a driving method thereof.
2. Description of the Related Art
A logic circuit processing a digital signal (hereinafter referred to as a digital circuit) is configured with one or a plurality of logic elements as a basic unit. The logic element is the one which provides one output corresponding to one or a plurality of inputs. Examples of the logic elements include an inverter, an AND, an OR, a NOT, a NAND, a NOR, a clocked inverter, a transmission gate and the like.
The logic element is configured with one or a plurality of circuit elements such as a transistor, a resistor and a capacitor. By operating the plurality of the circuit elements in accordance with a digital signal which is inputted to the logic element, a signal potential or a current which is to be supplied to a subsequent circuit is controlled.
Given as an example herein is an inverter as one of the logic elements. A configuration and an operation thereof are described concretely below.
A circuit diagram of a general inverter is shown in FIG. 13A. In FIG. 13A, IN means an inputted signal (input signal), and OUT means an outputted signal (output signal). Also, VDD and VSS mean power supply potentials and VDD is higher than VSS (VDD>VSS).
The inverter shown in FIG. 13A comprises a p-channel transistor 1301 and an n-channel transistor 1302. The gate (G) of the p-channel transistor 1301 and the gate (G) of the n-channel transistor 1302 are connected to each other, and the input signal IN is inputted to each gate. VDD in supplied to the first terminal of the p-channel transistor 1301, and VSS is supplied to the first terminal of the n-channel transistor 1302. Meanwhile, the second terminal of the p-channel transistor 1301 and the second terminal of the n-channel transistor 1302 are connected to each other and the output signal OUT is outputted from these second terminals to a subsequent circuit.
Note that, either the first terminal or the second terminal of each transistor corresponds to the source and the other corresponds to the drain. In the case of a p-channel transistor, a terminal having a higher potential is the source and a terminal having a lower potential is the drain, and in the case of an n-channel transistor, a terminal having a lower potential is the drain and a terminal having a higher potential is the source. Therefore, the first terminals of both transistors correspond to the sources (S) and the second terminals thereof correspond to the drains (D) in FIG. 13A.
Generally, as an input signal, a digital signal having binary potentials is utilized. Two circuit elements of the inverter are operated in accordance with a potential of the input signal IN, thereby controlling a potential of the output signal OUT. Next, the operations of the inverter as shown in FIG. 13A are described with reference to FIGS. 13B and 13C. Note that, in the FIGS. 13B and 13C, each circuit element is shown merely as a switch for clarification of the operating state.
FIG. 13B shows the operating state of each circuit element when the input signal IN has a potential on the high potential side. Here, the potential on the high potential side of the input signal IN is referred to as VDD′ (VDD′ VDD), and to simplify the explanation, it is assumed that a threshold voltage of an n-channel transistor 1302 (VTHn) is equal or higher than 0 (VTHn 0), and a threshold voltage of an p-channel transistor 1301 (VTHp) is equal or lower than 0 (VTHp≦0).
When the potential VDD′ is supplied to the gate of the p-channel transistor 1301, its gate voltage becomes VGS 0 because VDD′ VDD, and the p-channel transistor 1301 is thus turned OFF. Note that, the gate voltage corresponds to a voltage obtained by subtracting a potential of the source from a potential of the gate.
Meanwhile, when the potential VDD′ is supplied to the gate of the n-channel transistor 1302, its gate voltage becomes VGS>0 because VDD′>VSS, and the n-channel transistor 1302 is thus turned ON. Therefore, the power supply potential VSS is supplied to the subsequent circuit as a potential of the output signal OUT.
Next, the operating state of each circuit element when the input signal IN has a potential on the low potential side is shown in FIG. 13C. Here, the potential on the low potential side of the input signal IN is referred to as VSS′ (VSS′ VSS) and to simplify the explanation, it is assumed that a threshold voltage of the n-channel transistor 1302 (VTHn) is equal or higher than 0 (VTHn 0), and a threshold voltage of the p-channel transistor 1301 (VTHp) is equal or lower than 0 (VTHp 0).
When the potential VSS′ is supplied to the gate of the n-channel transistor 1302, its gate voltage becomes VGS 0 because VSS′ is equal or lower than VSS (VSS′ VSS), and the n-channel transistor 1302 is thus turned OFF.
Meanwhile, when the potential VSS′ is supplied to the gate of the p-channel transistor 1301, its gate voltage becomes VGS<0 because VSS′ is lower than VDD (VSS′<VDD), and the p-channel transistor 1301 is thus turned ON. Therefore, the power supply potential VDD is supplied to the subsequent circuit as a potential of the output signal OUT.
In this manner, each circuit element is operated in accordance with the potential of the input signal IN, thereby controlling the potential of the output signal OUT.
The operations of the inverter described above referring to FIGS. 13B and 13C axe the ones in the case where the binary potentials of the input signal IN (VDD′ and VSS′) are assumed to be in the relations of VDD′ VDD, and VSS′ VSS respectively. Hereinafter verified are the operations of the inverter as shown in FIG. 13A in the case of assuming that VDD′ is lower than VDD (VDD′<VDD) and VSS′ is higher than VSS (VSS′>VSS). Note that, VSS′<VDD′ is satisfied.
First, the operating state of each circuit element when the input signal IN has a potential on the high potential side VDD′ (VDD′<VDD) is shown in FIG. 14A. Here, to simplify the explanation, it is assumed that a threshold voltage of the n-channel transistor 1302 (VTHn) is equal or higher than 0 (VTHn 0) and a threshold voltage of the p-channel transistor 1301 (VTHp) is equal or lower than 0 (VTHp 0).
When the potential VDD′ is supplied to the gate of the p-channel transistor 1301, its gate voltage becomes VGS<0 because VDD′<VDD. Therefore, when |VGS|>|VTHp|, the p-channel transistor 1301 is turned ON. Meanwhile, when the potential VDD′ is supplied to the gate of the n-channel transistor 1302, its gate voltage becomes VGS>0 because VDD′ is higher than VSS (VDD′>VSS), thus the n-channel transistor 1302 is turned ON.
Therefore, as the p-channel transistor 1301 and the n-channel transistor 1302 are both turned ON, the potential of the output signal OUT does not become VSS even when the input signal IN has a potential on the high potential side, unlike the case shown in FIG. 13B.
A potential of the output signal OUT is determined by the current flowing in each transistor. In FIG. 14A, when VGS of the n-channel transistor 1302 is referred to as VGSn and VGS of the p-channel transistor 1301 is referred to as VGSp, |VGSn| is larger than |VGSp| (|VGSn|>|VGSp|). Therefore, the potential of the output signal OUT approaches closer to VSS than VDD when there is almost no difference between each transistor as to characteristics and channel width-to-length ratio (W/L). However, the potential of the output signal OUT may approach closer to VDD than VSS depending on a mobility, a threshold voltage and the channel width-to-length ratio (W/L) of each transistor. In this case, the digital circuit does not operate normally, leading to a high possibility of a malfunction. Further, it can cause a sequential malfunction in the subsequent digital circuit.
FIG. 14B shows the operating state of each circuit element when the input signal IN has a potential on the low potential side VSS′ (VSS′>VSS). To simplify the explanation, it is assumed that a threshold voltage of the n-channel transistor 1302 (VTHn) is equal or higher than 0 (VTHn 0) and a threshold voltage of the p-channel transistor 1301 (VTHp) is equal or lower than 0 (VTHp 0).
When the potential VSS′ is supplied to the gate of the n-channel transistor 1302, its gate voltage becomes VGS>0 because VSS′ is higher than VSS (VSS′>VSS). Therefore, when |VGS|>|VTHn|, the n-channel transistor 1302 is turned ON. Meanwhile, when the potential VSS′ is supplied to the gate of the p-channel transistor 1301, its gate voltage becomes VGS<0 because VSS′ is lower than VDD (VSS′<VDD), thus the p-channel transistor 1301 is turned ON.
Therefore, the p-channel transistor 1301 and the n-channel transistor 1302 are both turned ON depending on the values of VSS, VSS′ and VTHn. That means, unlike the case shown in FIG. 13C, a potential of the output signal OUT does not become VDD even when an input signal IN has a potential on the low potential side.
A potential of the output signal OUT is determined by the current flowing in each transistor. In FIG. 14B, when VGS of the n-channel transistor 1302 is referred to as VGSn and VGS of the p-channel transistor 1301 is referred to as VGSp, |VGSn| is smaller than |VGSp| (|VGSn|<|VGSp|). Therefore, the potential of the output signal OUT approaches closer to VDD than VSS when there is almost no difference between each transistor as to characteristics and channel width-to-length ratio (W/L). However, the potential of the output signal OUT can approach closer to VSS than VDD depending on a mobility, a threshold voltage and channel width-to-length ratio (W/L) of each transistor. In this case, the digital circuit does not operate normally, leading to a high possibility of a malfunction. Further, it can cause a sequential malfunction in the subsequent digital circuit.
As described above, in the inverter shown in FIG. 13A, an output signal OUT having a desired potential is obtained when the binary potentials VDD′ and VSS′ of the input signal IN are in the relations of VDD′ VDD, and VSS′ VSS respectively, thus a normal operation is obtained. However, when the binary potentials VDD′ and VSS′ of the input signal IN are in the relations of VDD′<VDD, and VSS′>VSS respectively, the output signal OUT having a desired potential is not obtained, thus the inverter may not operate normally.
The above case is not exclusively limited to the inverter, but can also be applied to other digital circuits. That is, when the binary potentials of the input signal IN is out of the predetermined range, the circuit elements of the digital circuit malfunction. Therefore, the output signal OUT having a desired potential can not be obtained and the digital circuit does not function normally.
A potential of the input signal supplied from a circuit or a wiring of a prior stage is not always an appropriate value for the digital circuit to operate normally. In this case, by adjusting the potential of the input signal by a level shifter, the digital circuit can be operated normally. However, a high-speed operation of the semiconductor device is frequently hindered by using the level shifter, because level shifters generally have problems in that the speed of rising and dropping of the potential of the output signal is low as each of the circuit elements operate in conjunction with each other such that the operation of one circuit element triggers the operations of other circuit elements.
It is also difficult to obtain a high-speed operation because transistors are not easily turned ON when the power supply voltage is low whereby the current is also reduced. On the other hand, when the power supply voltage is increased to obtain a high-speed operation, the power consumption is also increased.
Further, the current consumption is also increased since the n-channel transistor 1302 and the p-channel transistor 1301 are simultaneously turned ON and thus a short-circuit current flows in the transistors.
To solve the foregoing problems, it is proposed that in a level shifter circuit having a first input inverter and a second output inverter, a DC level of a signal which is inputted to the second inverter from the first inverter is converted by capacitors and a bias means (Reference Patent Document 1: Japanese Patent Laid-Open No. Hei 09-172367). However, in this circuit, each DC level conversion capacitor which is connected between the output terminal of the first inverter and the gate of each transistor configuring the second inverter is connected to a High-level power supply potential or a Low-level power supply potential at all times by the bias means. Therefore, the charge and discharge of these capacitors have damaging influence on the dynamic characteristics of the circuit (namely, causes a decrease in operation speed of the circuit), or the power consumption due to the charge and discharge of the capacitors is notably increased. Meanwhile, when there are variations in a threshold voltage of each transistor, it is difficult to match electrostatic capacitance of each capacitor to its corresponding transistor. Therefore, voltages of both terminals of the DC level conversion capacitors do not match the threshold voltage of the corresponding transistors, thus ON/OFF operation of the transistors may not be performed normally.